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JT6J15A-AS 2001-11-27 1 toshiba cmos digital integrated circuit silicon monolithic JT6J15A-AS row driver for a dot matrix lcd the JT6J15A-AS is a 80-channel-output row driver for a stn dot matrix lcd. the JT6J15A-AS features 28 v lcd drive voltage. the JT6J15A-AS is able to drive lcd panels with a duty ratio of up to 1/160. as the JT6J15A-AS is equipped with a built-in voltage divider resistor, power supply operation amplifier, four and six ? fold booster circuit, a contrast control circuit and a booster oscillator (oscillating capacitance is built in, and oscillating resistance is attached externally,) it is easy to structure a low power consumption lcd system by combining it with the jt6j14-as column driver. features display duty application : to 1/160 lcd drive signal : 80 data transfer : two different styles of 1-bit bidirectional can be selected (1) com80 com1 (2) com80 com1 operating temperature : ? 20 to 75c lcd drive output resistance : 1.5 k ? max (vo = 12.8 v, 1/7 to 1/14 bias) display ? off function : when /dspof is ?l?, all lcd drive outputs (o1 to o80) remain at the v ss /v 5 level lcd drive voltage : 11 to 28 v (maximum drive voltage = 30 v) power supply voltage : 2.7 to 5.5 v
JT6J15A-AS 2001-11-27 2 block diagram 1
JT6J15A-AS 2001-11-27 3 block diagram 2
JT6J15A-AS 2001-11-27 4 pin assignment
JT6J15A-AS 2001-11-27 5 pad coordinates scribe width : 80 140 m chip size : 4790 4850 m (including scribe width) number of pad : 124 pcs pad size : 100 m palette edge coordinates 1 : ? 2355, ? 2355 chip edge coordinates 1 : ? 2395, ? 2425 2 : ? 2355, 2355 2 : ? 2395, 2425 3 : 2355, 2355 3 : 2395, 2425 4 : 2355, ? 2355 4 : 2395, ? 2425 [unit: m] no pad name x point y point no pad name x point y point 1 v 4 ? 1950 ? 2139 34 osc2 2139 ? 1690 2 ms1 ? 1820 ? 2139 35 osc3 2139 ? 1560 3 ms2 ? 1690 ? 2139 36 o80 2139 ? 1430 4 v cc ? 1560 ? 2139 37 o79 2139 ? 1300 5 c5b ? 1430 ? 2139 38 o78 2139 ? 1170 6 c5a ? 1300 ? 2139 39 o77 2139 ? 1040 7 c4b ? 1170 ? 2139 40 o76 2139 ? 910 8 c4a ? 1040 ? 2139 41 o75 2139 ? 780 9 vout4 ? 910 ? 2139 42 o74 2139 ? 650 10 c3b ? 780 ? 2139 43 o73 2139 ? 520 11 c3a ? 650 ? 2139 44 o72 2139 ? 390 12 c2b ? 520 ? 2139 45 o71 2139 ? 260 13 c2a ? 390 ? 2139 46 o70 2139 ? 130 14 c1b ? 260 ? 2139 47 o69 2139 0 15 c1a ? 130 ? 2139 48 o68 2139 130 16 dio2 0 ? 2139 49 o67 2139 260 17 lp 130 ? 2139 50 o66 2139 390 18 fr 260 ? 2139 51 o65 2139 520 19 / dspof 390 ? 2139 52 o64 2139 650 20 v ss / v 5 520 ? 2139 53 o63 2139 780 21 dir 650 ? 2139 54 o62 2139 910 22 v dd 780 ? 2139 55 o61 2139 1040 23 di0 910 ? 2139 56 o60 2139 1170 24 di1 1040 ? 2139 57 o59 2139 1300 25 di2 1170 ? 2139 58 o58 2139 1430 26 di3 1300 ? 2139 59 o57 2139 1560 27 di4 1430 ? 2139 60 o56 2139 1690 28 di5 1560 ? 2139 61 o55 2139 1820 29 di6 1690 ? 2139 62 o54 2139 1950 30 di7 1820 ? 2139 63 o53 1950 2139 31 lck 1950 ? 2139 64 o52 1820 2139 32 dio1 2139 ? 1950 65 o51 1690 2139 33 osc1 2139 ? 1820 66 o50 1560 2139
JT6J15A-AS 2001-11-27 6 no pad name x point y point no pad name x point y point 67 o49 1430 2139 96 o20 ? 2139 1690 68 o48 1300 2139 97 o19 ? 2139 1560 69 o47 1170 2139 98 o18 ? 2139 1430 70 o46 1040 2139 99 o17 ? 2139 1300 71 o45 910 2139 100 o16 ? 2139 1170 72 o44 780 2139 101 o15 ? 2139 1040 73 o43 650 2139 102 o14 ? 2139 910 74 o42 520 2139 103 o13 ? 2139 780 75 o41 390 2139 104 o12 ? 2139 650 76 o40 260 2139 105 o11 ? 2139 520 77 o39 130 2139 106 o10 ? 2139 390 78 o38 0 2139 107 o9 ? 2139 260 79 o37 ? 130 2139 108 o8 ? 2139 130 80 o36 ? 260 2139 109 o7 ? 2139 0 81 o35 ? 390 2139 110 o6 ? 2139 ? 130 82 o34 ? 520 2139 111 o5 ? 2139 ? 260 83 o33 ? 650 2139 112 o4 ? 2139 ? 390 84 o32 ? 780 2139 113 o3 ? 2139 ? 520 85 o31 ? 910 2139 114 o2 ? 2139 ? 650 86 o30 ? 1040 2139 115 o1 ? 2139 ? 780 87 o29 ? 1170 2139 116 r 1 ? 2139 ? 910 88 o28 ? 1300 2139 117 r 2 ? 2139 ? 1040 89 o27 ? 1430 2139 118 r 3 ? 2139 ? 1170 90 o26 ? 1560 2139 119 vobak ? 2139 ? 1300 91 o25 ? 1690 2139 120 v 0 bias ? 2139 ? 1430 92 o24 ? 1820 2139 121 v 0 ? 2139 ? 1560 93 o23 ? 1950 2139 122 v 1 ? 2139 ? 1690 94 o22 ? 2139 1950 123 v 2 ? 2139 ? 1820 95 o21 ? 2139 1820 124 v 3 ? 2139 ? 1950
JT6J15A-AS 2001-11-27 7 pin functions pin name i / o functions level o1 to o80 output output for lcd drive signal v 0 to v ss / v 5 dio1, dio2 i / o input / output for shift data lp input (shift clock pulse) input for shift clock pulse fr input (frame) input for frame signal dir input (direction) input for data flow direction select / dspof input (display off) display off pin ?l?: display ? off mode, (o1 to o80) remain at the v ss / v 5 level. ?h?: display ? on mode, (o1 to o80) are operational. di0 to di7 input data bus: for contrast control usage contrast adjustments are variable between 128 stages with the di0 to di5 and d17 data. di6: when ?h?: stops the booster?s oscillation frequency and turns the power supply (v dd ) to the contrast controller off when ?l?: operates the booster circuit and contrast controller circuit lck input data bus loading clock synchronized during rising and loaded internally. r1 to r3 input bias set ? up pin (bias settings possible between 1 / 7 and 1 / 14) osc1 / osc2 input booster oscillation pin resistors connected to these pins when the internal clock is operating (100 k between osc1 and osc2). the clock is input to osc1 when the external clock is operating. osc3 output booster oscillating output pin the ocs3 pin is connected to another ic?s ocs1 when the booster?s oscillating frequency is shared with multiple connections. ms1 / ms2 input master / slave switching pin v dd to v ss / v 5 cna to cnb D terminal for connecting external condensers (n = 1 to 5) connect a booster capacitor which allows about c 2 = 3.3 f capacitance between cna and cnb. vout4 D booster voltage output pin (4 ? fold booster) connect vout4 and v cc when use of 4 ? fold booster. v cc D lcd drive voltage pin (operation amplifier drive voltage, 6 ? fold booster terminal) v dd D power supply for internal logic v ss / v 5 D power supply for internal logic vobak D voltage amplifier circuit v 0 , v 1 , v 2 , v 3 , v 4 , v 0 bias D power supply for lcd drive circuit connect an external capacitor which allows c 1 = 1.0 f capacitance or high to amp output. D
JT6J15A-AS 2001-11-27 8 relationship between fr, data input and output levels fr input data (dio1, dio2) / dspof output level h l h v 4 h h h v 0 bias l l h v 1 l h h v ss / v 5 (note) (note) l v ss / v 5 note: don?t care data input format data input terminals dir data transfer direction dio1 dio2 h o1 o80 input output l o80 o1 output input operation amplifier output control circuit ms1 ms2 / stop mode booster oscillations booster v 0 output v 1 , v 4 output v 2 , v 3 output l D booster stopped output cut, pd tr on output cut, pd tr on l (note 1) h slave mode (the booster circuit is driven and v cc voltage generated. v 0 , v 1 , v 2 , v 3 and v 4 are supplied from an external source) external clock booster stopped output cut, pd tr off (supplied from external source) output cut, pd tr on l oscillations stopped booster stopped output cut, pd tr on output cut, pd tr on output cut, pd tr on h l h master mode 1 (v 0 is output from the v cc voltage generating through driving the booster circuit. v 1 , v 2 , v 3 and v 4 are supplied from an external source) oscillations operating booster operating output on, pd tr off (supplied to internal / external sources) output cut, pd tr off (supplied from external source) output cut, pd tr on l oscillations stopped booster stopped output cut, pd tr on output cut, pd tr on h h h master mode 2 v 0 , v 1 , v 2 , v 3 and v 4 are output from the v cc voltage generating through driving the booster circuit.) oscillations operating booster operating output on, pd tr off (supplied to internal / external sources) output on, pd tr off (supplied to external source) pd: pull down note 1: connect to v dd or v ss / v 5
JT6J15A-AS 2001-11-27 9 timing diagram use of jt6j15a ? as 2 pcs (dir = ?h?) use of jt6j15a ? as 1 pc (dir = ?h?) absolute maximum ratings (ensure that the following conditions are maintained, v 0 v 1 v 2 v 3 v 4 v ss / v 5 = 0 v) characteristic symbol rating unit pin name power supply voltage (1) v dd ? 0.3 to 6.0 v v dd power supply voltage (2) v cc v dd to 30.0 v v cc input voltage v in ? 0.3 to v dd + 0.3 v (note 2) operating temperature t opr ? 20 to 75 c D storage temperature t stg ? 40 to 125 c D note 2: fr, lp, dir, dio1, dio2, di0 to di7, lck, r1 to r3, / dspof
JT6J15A-AS 2001-11-27 10 electrical characteristics dc characteristics 1 (unless otherwise noted, v ss = 0 v, v dd = 2.7 to 5.5 v, v 0 = 11 to 28 v, ta = ? 20 to 75c) item symbol test circuit test condition min typ. max unit pin name supply voltage (1) v dd D D 2.7 5.0 5.5 v v dd supply voltage (2) v 0 D v cc v0 11 D 28 v v 0 supply voltage (3) v cc D v cc v0 11 D 28 v v cc ?h? level v ih D D 0.8 v dd D v dd input voltage ?l? level v il D D 0 D 0.2 v dd v (note 3) ?h? level v oh D i oh = ? 0.5 ma v dd ? 0.5 D v dd output voltage ?l? level v ol D i ol = 0.5 ma 0 D 0.5 v dio1, dio2 ?h? level r oh D v out = v0 ? 0.5 v (note 4) D D 1.5 r om D v out = v1 0.5 v (note 4) D D 1.5 ?m? level r om D v out = v4 0.5 v (note 4) D D 1.5 output resistance ?l? level r ol D v out = v ss / v 5 + 0.5 v (note 4) D D 1.5 k ? o1 to o80 input current iil1 D v in = 0 to v dd ? 1.0 D 1.0 a (note 3) output voltage (with a 4 ? fold booster) v o1 D v dd = 5.0 v (note 5) 17.64 D D output voltage (with a 6 ? fold booster) v o2 D v dd = 3.0 v (note 5) 14.0 D D v v cc D v dd = 5.0 v when operating (note 6) D 1.1 1.5 i dd ope D v dd = 3.0 v when operating (note 7) D 1.2 1.8 ma i dd leak D v dd = 5.5 v when no operating D D 1.0 v dd i 0 bias ope D when operating (note 8) D 1.0 25 v 0 bias current consumption i cc leak D v 0 = 15.0 v when no operating (note 9) D D 1.0 a v cc note 3: fr, lp, dir, dio1, dio2, di0 to di7, lck, r1 to r3, / dspof note 4: v 0 = 12.8 v, 1 / 7 to 1 / 14 bias note 5: iload = 450 a, external c 2 = 3.3 f, when using com 1 pc ta = 25 c, op ? amp on note 6: oscillation resistance = 100 k ? , dc / dc on, op ? amp on, 1 / 10 bias, contrast max flp = 11.2 khz, ffr = 35 hz, ffp = 70 hz, v dd = 5.0 v, 4 booster, no load note 7: oscillation resistance = 100 k , dc / dc on, op ? amp on, 1 / 10 bias, contrast max flp = 11.2 khz, ffr = 35 hz, ffp = 70 hz, v dd = 3.0 v, 6 booster, no load note 8: lcd drive current: ffr = 35 hz, flp = 11.2 khz, ffp = 70 hz, 1 / 10 bias, no load, ms1 = ?l?, / stop = ?l? note 9: ms1 = ?l?, / stop = ?l? f fp : screen switching frequency
JT6J15A-AS 2001-11-27 11 dc characteristics 2 load regulations characteristics 1 no load / max load offset test conditions: v cc = 18 v (outside applied voltage), contrast = 62 (di1 to di5 = ?h?, di0, di7 = ?l?), external capacitor for amp: c 1 = 1.0 f gain resistance = 4 times (3r 0 , r 0 ), 1 / 10 bias, v dd = 5.0 v, ta = ? 20 to 75c, the v 1 to v 4 offset spec is defined toward the ideal voltage calculated from the v 0 voltage. offset specified value no load max load max load (reverse electric current) min max min max min max unit v 0 14.6 15.6 14.50 15.50 D D v v 1 ? 100 90 ? 110 75 ? 110 110 mv v 2 ? 65 65 ? 50 75 ? 110 110 mv v 3 ? 70 70 ? 85 50 ? 110 110 mv v 4 ? 55 50 ? 45 65 ? 110 110 mv x ? 220 190 ? 255 145 D D mv y ? 120 130 ? 170 85 D D mv ? v ? 210 190 ? 300 120 D D mv load conditions no load max load max load (reverse electric current) unit i 0 0 ? 300 D a i 1 0 ? 50 50 a i 2 0 200 ? 100 a i 3 0 ? 200 100 a i 4 0 50 ? 50 a non ? lighting bias x = (v 1 ? v 2 ) ? (v 0 ? v 1 ) y = (v 3 ? v 4 ) ? (v 4 ? v ss ) vom balance ? v = x + y
JT6J15A-AS 2001-11-27 12 v0 to v4 are specified as follows when the v0 voltage is set to the maximum voltage for the contrast with the di0 to di7 data bus set to ?h?. bias set ? up value r 1 r 2 r 3 v 1 v 2 v 3 v 4 1 / 7 h h h 6 / 7v0 5 / 7v0 2 / 7v0 1 / 7v0 1 / 8 l h h 7 / 8v0 6 / 8v0 2 / 8v0 1 / 8v0 1 / 9 h l h 8 / 9v0 7 / 9v0 2 / 9v0 1 / 9v0 1 / 10 l l h 9 / 10v0 8 / 10v0 2 / 10v0 1 / 10v0 1 / 11 h h l 10 / 11v0 9 / 11v0 2 / 11v0 1 / 11v0 1 / 12 l h l 11 / 12v0 10 / 12v0 2 / 12v0 1 / 12v0 1 / 13 h l l 12 / 13v0 11 / 13v0 2 / 13v0 1 / 13v0 1 / 14 l l l 13 / 14v0 12 / 14v0 2 / 14v0 1 / 14v0 ac characteristics 1 test conditions: t c (one lp signal cycle) = t cwh + t cwl + t r + t f (unless otherwise noted, v ss = 0 v, v dd = 2.7 to 5.5 v, v cc = 11 to 28 v, ta = ? 20 to 75c) item symbol test condition min typ. max unit t cwh lp 30 D D ns lp pulse width t cwl lp 1 D D s data set ? up time t dsu dio1, dio2 30 D D data hold time t dhd dio1, dio2 5 D D lp rise / fall time t r , t f lp, fr, dio1, dio2 D D 50 output delay time (note 11) t pd dio1, dio2 20 D 500 ns oscillating frequency osc1 (note 12) 25.5 D 42.5 external clock frequency f osc osc3 25.5 D 42.5 khz note 11: c l = 10 pf note 12: external resistance = 100 k ? (between osc1 and osc2)
JT6J15A-AS 2001-11-27 13 ac characteristics 2 test conditions 1 (unless otherwise noted, v ss = 0 v, v dd = 3.0 v 10%, v cc = 11 to 28 v, ta = ? 20 to 75c) item symbol test condition min typ. max unit enable rise / fall time t er / t ef D D D 25 ns enable pulse width pwel D 60 D D ns data set ? up time t ds D 60 D D ns data hold time t dhw D 10 D D ns test conditions 2 (unless otherwise noted, v ss = 0 v, v dd = 5.0 v 10%, v cc = 11 to 28 v, ta = ? 20 to 75c) item symbol test condition min typ. max unit enable rise / fall time t er / t ef D D D 20 ns enable pulse width pwel D 60 D D ns data set ? up time t ds D 60 D D ns data hold time t dhw D 10 D D ns
JT6J15A-AS 2001-11-27 14 s ys t em di agram (120 80 dots)
JT6J15A-AS 2001-11-27 15 system diagram (240 80 dots)
JT6J15A-AS 2001-11-27 16 system diagram (240 160 dots)
JT6J15A-AS 2001-11-27 17 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases this can cause the device to malfunction. this is especially true for devices in which the surface (back), or side of the chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. exposure to light both during regular operation and during inspection must be taken into account. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707ebm restrictions on product use

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